1. Field of the Invention
This invention relates to a display control system for use in a display unit such as a liquid crystal display unit and a CRT display unit, and in particular to such a display control system which can implement a gray-scale display.
2. Prior Art
FIG. 1 shows one conventional liquid crystal display unit 10. The display unit 10 comprises a CPU (Central Processing Unit) 1, a display controller 2, a video memory 3 and a liquid crystal display module 4. The liquid crystal display module 4 includes, as shown in FIG. 2, a liquid crystal display panel 5 and a panel driver circuit 6 provided for driving the display panel 5. The liquid crystal display panel 5 has, for example, 640 horizontal electrodes (column electrodes) and 200 vertical electrodes (row electrodes) for displaying an image composed of a 640.times.200 dot matrix. The liquid crystal display panel 5 is divided into two display blocks A and B of an identical construction which are independently driven, the liquid crystal display panel 5 being commercially available. The column electrodes of the display block A are driven by a circuit comprising a 640-bit shift register 7a, a 640-bit latch circuit 8a and an electrode driving circuit 9a, while the column electrodes of the display block B are driven by another circuit comprising a 640-bit shift register 7b, a 640-bit latch circuit 8b and an electrode driving circuit 9b. The row electrodes of the display blocks A and B are driven by a circuit comprising a 100-bit shift register 11 and an electrode driving circuit 12.
With this construction, the CPU 1 (FIG. 1) stores image data into the video memory 3 and then outputs a display command to the display controller 2. In response to this display command, the display controller 2 reads the image data from the video memory 3 and forms, in accordance with the read image data, display data LDa and LDb in the form of serial data. The display controller 2 then outputs the display data LDa and LDb to the liquid crystal display module 4 together with a shift clock signal SCK. As a result, the display data LDa and LDb are sequentially stored respectively into the shift registers 7a and 7b. When the display data LDa and LDb are fully loaded onto the shift register 7a and 7b, respectively, the display controller 2 outputs a latch clock signal LC and a frame signal FRM. When the signals LC and FRM are outputted, the data contained in the shift registers 7a and 7b are loaded onto the latch circuits 8a and 8b and at the same time a "1" signal is stored into the first-bit stage of the shift register 11, whereby a display of dots is made on each of the 1st (uppermost) and 101st rows of the display panel 5. The display controller 2 then outputs the data LDa and LDb for displaying dots on the 2nd and 102nd rows of the display panel 5 together with the shift clock signal SCK, and outputs the latch clock signal LC when the data LDa and LDb (640 bits) are fully loaded onto the shift registers 7a and 7b. As a result, the data contained in the shift registers 7a and 7b are stored into the latch circuits 8a and 8b and at the same time a "1" signal is stored into the second bit-stage of the shift register 11, whereby a display of dots is made on each of the 2nd and 102nd rows of the display panel 5. And thereafter, an operation similar to the above is repeatedly carried out to display dots on the display panel 5. The aforesaid frame signal FRM is outputted at the beginning of each frame scanning. The frame frequency of this display unit 10 is set to 70 Hz.
To display an image in gray-scale with the above-described liquid crystal display unit 10, one of the following methods have conventionally been taken. According to one of the methods, the voltages applied to the display panel 5 to display the respective dots are individually controlled as disclosed in Japanese Patent Application Laid-Open No. 59-149393. With this prior art liquid crystal display apparatus, the effective voltage applied to each dot of the liquid crystal display module is changed as shown at E, F and G in FIG. 6 of the published document. In FIG. 6, the effective voltage V.sub.on shown at F for displaying a dot at the highest intensity level is represented by: EQU V.sub.on.sup.2 =(1/N)V.sub.0.sup.2 +[(N-1)/N](V.sub.0 /a).sup.2
Wherein a is equal to (N.sup.1/2 +1). Also, the effective voltage V.sub.off shown at F for displaying a dot at the lowest intensity is represented by: EQU V.sub.off.sup.2 =(1/N)(1-2/a).sup.2 V.sub.0.sup.2 +[(N-1)/N](V.sub.0 /a).sup.2
And, the effective voltage V.sub.h shown at E for displaying a dot of a half tone is represented by: EQU V.sub.h.sup.2 =V.sub.0.sup.2 /2N+(1/2N)(1-2/a).sup.2 V.sub.0.sup.2 +[(N-1)/N]V.sub.0 /a).sup.2
According to another conventional method, the pulse widths of the voltages applied to the display panel 5 to display the respective dots are individually controlled.
In either of the above two cases, a circuit for performing such a control must have been additionally provided within the liquid crystal display module 4, which has significantly increased the costs thereof since such a control circuit is very complicated.